module clok_div(clk_1kHz,rst,clk_4Hz,clk_1Hz,clk_10Hz);
// * 实现三种分频 1000分频，250 分频，100分频

    input clk_1kHz;
    input rst;
    output reg clk_1Hz;
	 output reg clk_4Hz;
	 output reg clk_10Hz;
	 reg[8:0] cnt_1hz;
	 reg[6:0] cnt_4hz;
	 reg[5:0] cnt_10hz; 
	 
	 //1kHz -> 10Hz 100分频
	always @(posedge clk_1kHz or negedge rst)
		 if(!rst) begin
			  cnt_10hz    <= 6'b000000;
			  clk_10Hz    <= 1'b0;
		 end
		 else if(cnt_10hz < 6'b110000) begin
			  cnt_10hz <= cnt_10hz + 1'b1;
		 end
		 else begin
			  cnt_10hz <= 6'b000000;
			  clk_10Hz <= ~clk_10Hz;
		 end
		 
	 
	 //1kHz -> 4Hz 250分频
	always @(posedge clk_1kHz or negedge rst)
		 if(!rst) begin
			  cnt_4hz <= 7'b0000000;
			  clk_4Hz <= 1'b0;
		 end
		 else if(cnt_4hz < 7'b1111100) begin
			  cnt_4hz <= cnt_4hz + 1'b1;
		 end
		 else begin
			  cnt_4hz <= 7'b0000000;
			  clk_4Hz <= ~clk_4Hz;
		 end
		 
	 //1kHz -> 1Hz 1000分频
	always @(posedge clk_1kHz or negedge rst)
		 if(!rst) begin
			  cnt_1hz <= 9'b000000000;
			  clk_1Hz <= 1'b0;
		 end
		 else if(cnt_1hz < 9'b111110010) begin
			  cnt_1hz <= cnt_1hz + 1'b1;
		 end
		 else begin
			  cnt_1hz <= 9'b000000000;
			  clk_1Hz <= ~clk_1Hz;
		 end

endmodule